Electronically Programmable Read-Only Memories (EPROMs) have been used for a number of applications for many years, and OTP EPROMs have been used as an effective, low-cost technology for providing embedded nonvolatile memory. These nonvolatile memories are generally formed using an OTP element, cell, or transistor. Typically, this OTP cell is (for example) an enhancement-mode PMOS with a floating gate (typically made of polysilicon). It can be electrically programmed and can be erased through expose to light in the ultraviolet (UV) spectrum. Typically, a programmed OTP cell is an “on cell” and will conduct current, while an erased OTP cell is an “off cell” and does not conduct current. As shown in the example of FIG. 1, an EPROM is generally comprised of an array 100 of bit cells 102-11 to 102-NN, which can be erased by UV light. These bit cells 102-11 to 102-NN are accessed through word lines WL1 to WLN and bit lines BL1 to BL-N; in particular, sense amplifier 104-1 to 104-N are used to read the array 100 through the bit lines BL-1 to BL-N.
To accomplish the nonvolatile functionality of the array 100, each bit cell employs an OTP cell or transistor. Turning to FIG. 2, an example of one of the bit cells 102-11 to 102-NN (hereinafter 102) which is coupled to one of the word lines WL1 to WLN (hereinafter WL) and one of the bit lines BL1 to BLN (hereinafter BL). As shown, the bit cell 102 generally comprises a transistor Q1 (which can be, for example, a PMOS transistor) and an OTP cell 202 (which can, for example, be a PMOS OTP cell).
Turning to FIGS. 3A to 3G, the layout for the bit cell 102 of FIG. 2 on substrate 311 can be seen. As shown, the bit cell 102 employs an active area 302 that is used for both the transistor Q1 (which uses portion 306) and OTP cell 202 (which uses portion 304). Gates 308 and 310 are formed over these portions 304 and 306 (respectively), separating the source/drain regions 316/318 and 326/328 (respectively). These gates 312 and 322 are generally formed of a gate dielectric layer 314 and 344, respectively, (which can, for example, be silicon dioxide or a high-K dielectric, like halfnium oxide) and a gate electrode 312 and 322, respectively (which may be a single or dual layer polysilicon gate) that are surrounded by a interlayer dielectric 320 (which may be, for example, silicon dioxide). The drain of the OTP cell 202 (i.e., source/drain region 316) is coupled to the bit BL (which is formed by a portion of metal layer 346) through vias 336, 338 and 340 and strap (which is generally formed by a portion of metal layer 334), and the source of transistor Q1 (i.e., source/drain region 328) is electrically coupled to supply voltage VDD (which is supplied on metal layer 334) through vias 336, while substrate diffusion 344 (which generally functions as body contacts) is electrically coupled to supply voltage VDD through vias 342.
There are some drawbacks for this arrangement. OTP cells are commonly used for circuit trimming, die ID, and other areas requiring relatively small amounts of data storage. High speed is usually not required when reading a typical OTP. For an existing process, to achieve near 0 Defect Parts Per Million (dppm), the process corners should cover more than 6 standard deviations or 6-sigma. A 6-sigma process is one in which 99.99966% (i.e., 3.4 defects per million) of the products manufactured are expected to be free of defects after 10 years. Tests and measurements show that after 10 years, the programmed OTP bit cell is very weak due to charge loss from the floating gate. For example, the OTP transistor “on cell” current, ION, can drop from about 25 uA to less than 5 uA after 10 years. The drop in current ION significantly slows down the sense amplifier (i.e., 104-1) sensing speed. Thus, the bit cell 102 (being a single-ended cell) will become significantly slower over time. To compensate for this degradation over time, a differential sensing implementation can be used. When sensing a single cell (i.e., bit cell 102) differentially, the selected bit line is compared with a reference voltage or current. So, a very accurate reference is used for the comparison, which can be very difficult to accomplish and which can consume a large amount of area. Another way to perform differential sensing, which avoids the very accurate reference, is to use two bit cells (i.e., bit cell 102) for one bit of data, where one bit cell is programmed with true data and the other bit cell is programmed with complement data. However, this approach uses twice the area of a single bit cell. Therefore, there is a need for an improved bit cell.
Some examples of other conventional systems are: U.S. Pat. No. 6,509,606; U.S. Pat. No. 6,639,270; U.S. Pat. No. 6,770,933; U.S. Pat. No. 6,897,113; U.S. Pat. No. 7,402,874; U.S. Pat. No. 7,602,029; U.S. Pat. No. 7,675,106; U.S. Patent Pre-Grant Publ. No. 2002/0175353.